Publications
2026
PACT 2026
HARMONY: Cooperative Memory Scheduling for CXL Memory Systems
2026 International Conference on Parallel Architectures and Compilation Techniques (PACT 2026) (Poster)
MICRO 2026
Don't Get Stuck in Traffic: A Case for Contention-Aware Translation Offloading
59th IEEE/ACM International Symposium on Microarchitecture (MICRO 2026)
DATE 2026
Boosting LLC Bandwidth Utilization in GPUs through Adaptive Fine-Grained Data Migration
2026 Design, Automation and Test in Europe Conference (DATE 2026)
DATE 2026
Braid-ZNS: Leveraging Zone Random Write Area for Efficient In-Storage Compression on ZNS SSDs
2026 Design, Automation and Test in Europe Conference (DATE 2026)
DATE 2026
Lupin: Spatial Resource Stealing with Outlier-First Encoding for Mixed-Precision LLM Acceleration
2026 Design, Automation and Test in Europe Conference (DATE 2026)
DATE 2026
Scrooge: Accelerating Attention Inference in LLMs via Early Termination Mechanism
2026 Design, Automation and Test in Europe Conference (DATE 2026)
IEEE CAL
Clover: Storage-Efficient Page Table Replication in Wafer-Scale GPUs
IEEE Computer Architecture Letters
IEEE CAL
NeuroMTA: Programmable Simulation Framework for Multi-Tile NPU Architectures
IEEE Computer Architecture Letters
IEEE CAL
IEEE TPDS
Sparsity-Aware Fault Tolerance for Reliable CNN Inference on GPUs
IEEE Transactions on Parallel and Distributed Systems
2025
PACT 2025
LibraPIM: Dynamic Load Rebalancing to Maximize Utilization in PIM-Assisted LLM Inference Systems
2025 International Conference on Parallel Architectures and Compilation Techniques (PACT 2025)
MICRO 2025
Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs
58th IEEE/ACM International Symposium on Microarchitecture (MICRO 2025)
MICRO 2025
SoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications
58th IEEE/ACM International Symposium on Microarchitecture (MICRO 2025)
ISCA 2025
Avalanche: Optimizing Cache Utilization via Matrix Reordering for Sparse Matrix Multiplication Accelerator
2025 International Symposium on Computer Architecturee (ISCA 2025)
DAC 2025
PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup
2025 Design Automation Conference (DAC 2025)
ICCD 2025
DDLM: Demand-Aware Dynamic Link Width Management for Energy-Efficient CXL Memory
The 43rd IEEE International Conference on Computer Design (ICCD 2025)
ICCD 2025
Minimizing Read Disturb via Localized Page Allocation for Modern NAND Flash-Based SSDs
The 43rd IEEE International Conference on Computer Design (ICCD 2025)
DATE 2025
Buddy ECC: Making Cache Mostly Clean in CXL-Based Memory Systems for Enhanced Error Correction at Low Cost
2025 Design, Automation & Test in Europe Conference & Exhibition (DATE 2025)
DATE 2025
Improving Address Translation in Tagless DRAM Cache by Caching PTE Pages
2025 Design, Automation & Test in Europe Conference & Exhibition (DATE 2025)
DATE 2025
SPB: Towards Low-Latency CXL Memory via Speculative Protocol Bypassing
2025 Design, Automation & Test in Europe Conference & Exhibition (DATE 2025)
DATE 2025
Zebra: Leveraging Diagonal Attention Pattern for Vision Transformer Accelerator
2025 Design, Automation & Test in Europe Conference & Exhibition (DATE 2025)
IEEE Access
IEEE Access
ITC-CSCC 2025
Evaluating Performance of Modern GPU with Partitioned Last-Level Caches
40th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2025)
ITC-CSCC 2025
Outlier Matters: A Statistical Analysis of LLM Tensor Distributions and Quantization Effects
40th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2025)
ITC-CSCC 2025
Tournament Warp Scheduling: A Dynamic Policy Selector Exploiting Sub-cores in GPUs
40th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2025)
ITC-CSCC 2025
Towards Efficient Compression in ZNS SSDs: Analysis of Inherent Attributes and Applicability
40th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2025)
ICEIC 2025
Evaluating Data Compression Algorithms and Their Impact on NAND Flash-Based SSDs
2025 International Conference on Electronics, Information, and Communication (ICEIC)
ICEIC 2025
Redefining PIM Architecture with Compact and Power-Efficient Microscaling
2025 International Conference on Electronics, Information, and Communication (ICEIC)
Paper:
2024
MICRO 2024
A Case for Speculative Address Translation with Rapid Validation for GPUs
57th IEEE/ACM International Symposium on Microarchitecture (MICRO 2024)
Paper:
Slides:
MICRO 2024
Distributed Page Table: Harnessing Physical Memory as an Unbounded Hashed Page Table
57th IEEE/ACM International Symposium on Microarchitecture (MICRO 2024)
Paper:
Slides:
PACT 2024
Rethinking Page Table Structure for Fast Address Translation in GPUs: A Fixed-Size Hashed Page Table
2024 International Conference on Parallel Architectures and Compilation Techniques (PACT 2024)
Paper:
Slides:
DAC 2024
Don't Cache, Speculate!: Speculative Address Translation for Flash-based Storage Systems
2024 Design Automation Conference (DAC 2024) (Poster)
IEEE Access
IEEE Transactions on Magnetics
Enhanced Positional SECDED: Achieving Maximal Double-Error Correction in Racetrack Memories
IEEE Transactions on Magnetics ( Volume: 60, Issue: 3, March 2024)
Paper:
ICCE-ASIA 2024
Performance Characterization of CXL Memory Expander: Impact on Read and Write Latencies
24’ International Conference on Consumer Electronics (ICCE-ASIA 2024)
Slides:
ISOCC 2024
A Two-level Tracking Mechanism to Mitigate RowHammer Attacks
The 21st International SoC Design Conference (ISOCC 2024)
ISOCC 2024
Leveraging Algorithm-based Fault Tolerance for Propagation Error Detection in NPUs
The 21st International SoC Design Conference (ISOCC 2024)
ITC-CSCC 2024
Analysis of L2P Map cache size and hash function correlation in NAND Flash-based SSDs
The 39th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2024)
2023
PACT 2023
SparseFT: Sparsity-aware Fault Tolerance for Reliable CNN Inference on GPUs
2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) (Poster)
Paper:
DAC 2023
CRAN: A Computational Redundancy-aware Accelerator for Convolutional Neural Networks
2023 Design Automation Conference (DAC 2023) (Poster)
ACML 2023
Facto-CNN: Memory-Efficient CNN Training with Low-rank Tensor Factorization and Lossy Tensor Compression
Proceedings of the 15th Asian Conference on Machine Learning (ACML)
Paper:
ICCD 2023
Conveyor: Towards Asynchronous Dataflow in Systolic Array to Exploit Unstructured Sparsity
2023 IEEE 41st International Conference on Computer Design (ICCD)
Paper:
Slides:
IEEE Access
On the Positional Single Error Correction and Double Error Detection in Racetrack Memories
IEEE Access ( Volume: 11)
Paper:
ISOCC 2023
Improving Performance and Energy-efficiency of DNN Accelerators with STT-RAM Buffers
2023 20th International SoC Design Conference (ISOCC)
Paper:
Slides:
ITC-CSCC 2023
CAESAR: A CNN Accelerator Exploiting Sparsity and Redundancy Pattern
2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)
Paper:
Slides:
ITC-CSCC 2023
In-Cache Processing with Power-of-Two Quantization for Fast CNN Inference on CPUs
2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)
Paper:
ITC-CSCC 2023
Why Address Translation Matter?: Analyzing Page Access Patterns in NAND Flash-Based SSDs
2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)
Paper:
2022
DAC 2022
Constructing Large Buffers with Heterogeneous STT-RAM Cells for DNN Accelerators
2022 Design Automation Conference (DAC 2022) (Poster)
DAC 2022
Don't open row: rethinking row buffer policy for improving performance of non-volatile memories
2022 Design Automation Conference (DAC 2022)
Paper:
Slides: