Publications



2020

KSCI 2020

Memory System
Dynamic Rank Subsetting with Data Compression

Journal of the Korea Society of Computer and Information, Volume 25 Issue 4, pp.1-9, 2020

  • Seokin Hong

    • Paper: Paper Icon

    KSCI 2020

    Memory System
    Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches

    Journal of the Korea Society of Computer and Information, Volume 25 Issue 3, pp.1-9, 2020

  • Seokin Hong

    • Paper: Paper Icon



    2019

    Top-tier

    MICRO 2019

    Memory System
    Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads

    MICRO ‘52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

  • Seokin Hong

  • Bulent Abali

  • Alper Buyuktosunoglu

  • Michael B. Healy

  • Prashant J. Nair

    • Paper: Paper Icon

    Top-tier

    ASPLOS 2019

    Memory System
    Split-CNN: Splitting Window-based Operations in Convolutional Neural Networks for Memory System Optimization

    ASPLOS ‘19: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems

  • Tian Jin

  • Seokin Hong

    • Paper: Paper Icon

    SCIE

    IEEE VLSI

    Memory System
    Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

  • Wonyoung Lee

  • Mincheol Kang

  • Seokin Hong

  • Soontae Kim

  • Seokin Hong

    • Paper: Paper Icon

    KSC 2019

    Memory System
    Analyzing the Performance Overhead of Secure Memory

    Korea Software Congress(KSC) 2019

  • Chanhui Seok

  • Seokin Hong

    • Paper: Paper Icon

    KSC 2019

    Other
    Performance Characterization of STAR RNA-seq aligner on Multi-core Processor

    Korea Software Congress(KSC) 2019

  • Gwangeun Byeon

  • Seokin Hong

    • Paper: Paper Icon



    2018

    Top-tier

    MICRO 2018

    Memory System
    Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads

    2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

  • Seokin Hong

  • Prashant Jayaprakash Nair

  • Bulent Abali

  • Alper Buyuktosunoglu

  • Kyu-Hyoun Kim

  • Michael Healy

    • Paper: Paper Icon



    2017

    Top-tier

    HPCA 2017

    Memory System
    Partial Row Activation for Low-Power DRAM System

    2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)

  • Yebin Lee

  • Hyeonggyu Kim

  • Seokin Hong

  • Soontae Kim

    • Paper: Paper Icon

    MEMSYS 2017

    Memory System
    CramSim: controller and memory simulator

    MEMSYS ‘17: Proceedings of the International Symposium on Memory Systems

  • Michael Healy

  • Seokin Hong

    • Paper: Paper Icon



    2016

    SCI

    IEEE TC 2016

    Memory System
    Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures

    IEEE Transactions on Computers ( Volume: 65, Issue: 10, 01 October 2016)

  • Seokin Hong

  • Soontae Kim

    • Paper: Paper Icon



    2015

    SCI

    IEEE TC 2015

    Memory System
    A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU

    IEEE Transactions on Computers ( Volume: 64, Issue: 9, 01 September 2015)

  • Seokin Hong

  • Soontae Kim

    • Paper: Paper Icon

    SCI

    IEEE TC 2015

    Memory System
    Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho

    IEEE Transactions on Computers ( Volume: 64, Issue: 6, 01 June 2015)

  • Tayyeb Mahmood

  • Seokin Hong

  • Soontae Kim

    • Paper: Paper Icon



    2014

    Major

    ICCD 2014

    Memory System
    Ternary cache: Three-valued MLC STT-RAM caches

    2014 IEEE 32nd International Conference on Computer Design (ICCD)

  • Seokin Hong

  • Soontae Kim

  • Jongmin Lee

    • Paper: Paper Icon



    2013

    Top-tier

    HPCA 2013

    Memory System
    Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling

    2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

  • Tayyeb Mahmood

  • Soontae Kim

  • Seokin Hong

    • Paper: Paper Icon

    Top-tier

    HPCA 2013

    Memory System
    Skinflint DRAM system: Minimizing DRAM chip writes for low power

    2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

  • Yebin Lee

  • Soontae Kim

  • Seokin Hong

  • Jongmin Lee

    • Paper: Paper Icon

    Major

    DATE 2013

    Computer Architecture
    AVICA: An access-time variation insensitive L1 cache architecture

    2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)

  • Seokin Hong

  • Soontae Kim

    • Paper: Paper Icon



    2011

    Top-tier

    MICRO 2011

    Memory System
    Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits

    MICRO-44: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

  • Soontae Kim

  • Jongmin Lee

  • Jesung Kim

  • Seokin Hong

    • Paper: Paper Icon

    Major

    LPED 2011

    Memory System
    TLB index-based tagging for cache energy reduction

    IEEE/ACM International Symposium on Low Power Electronics and Design

  • Jongmin Lee

  • Seokin Hong

  • Soontae Kim

    • Paper: Paper Icon



    2010

    Major

    ICCD 2010

    Computer Architecture
    Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU

    2010 IEEE International Conference on Computer Design

  • Seokin Hong

  • Soontae Kim

    • Paper: Paper Icon



    2009

    ISVLSI 2009

    Computer Architecture
    TEPS: Transient Error Protection Utilizing Sub-word Parallelism

    2009 IEEE Computer Society Annual Symposium on VLSI

  • Seokin Hong

  • Soontae Kim

    • Paper: Paper Icon