Publications
2022
IEEE Access
Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation
IEEE Access ( Volume: 10)
Paper:
IEEE Access
On-the-Fly Lowering Engine: Offloading Data Layout Conversion for Convolutional Neural Networks
IEEE Access ( Volume: 10)
Paper:
IEEE Access
Electronics 2022
Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches
Electronics 2022
Paper:
ICCE-Asia 2022
Virtual PTE Storage: Repurposing Last-level Cache to Accelerate Address Translation for Big Data Workloads
2022 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)
Paper:
2021
Sensors 2022
IEEE TC 2021
CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems
IEEE Transactions on Computers ( Volume: 70, Issue: 7, 01 July 2021)
Paper:
KSCI 2021
Exploiting Hardware Events to Reduce Energy Consumption of HPC Systems
Journal of The Korea Society of Computer and Information, Volume 26 Issue 8, pp.1-11, 2021.
Paper:
ICEIC 2021
Proactive Dead Block Eviction for Reducing Write Latency in STT-MRAM Caches
2021 International Conference on Electronics, Information, and Communication (ICEIC)
Paper:
2020
ICCD 2020
ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches
2020 IEEE 38th International Conference on Computer Design (ICCD)
Paper:
KSCI 2020
Dynamic Rank Subsetting with Data Compression
Journal of the Korea Society of Computer and Information, Volume 25 Issue 4, pp.1-9, 2020
Paper:
KSCI 2020
Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches
Journal of the Korea Society of Computer and Information, Volume 25 Issue 3, pp.1-9, 2020
Paper:
2019
MICRO 2019
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads
MICRO ‘52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
Paper:
ASPLOS 2019
Split-CNN: Splitting Window-based Operations in Convolutional Neural Networks for Memory System Optimization
ASPLOS ‘19: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
Tian Jin
Paper:
IEEE VLSI
Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Paper:
KSC 2019
Analyzing the Performance Overhead of Secure Memory
Korea Software Congress(KSC) 2019
Chanhui Seok
Paper:
KSC 2019
Performance Characterization of STAR RNA-seq aligner on Multi-core Processor
Korea Software Congress(KSC) 2019
Paper:
2018
MICRO 2018
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Paper:
2017
HPCA 2017
Partial Row Activation for Low-Power DRAM System
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
Paper:
MEMSYS 2017
CramSim: controller and memory simulator
MEMSYS ‘17: Proceedings of the International Symposium on Memory Systems
Michael Healy
Paper:
2016
IEEE TC 2016
Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures
IEEE Transactions on Computers ( Volume: 65, Issue: 10, 01 October 2016)
Soontae Kim
Paper:
2015
IEEE TC 2015
A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU
IEEE Transactions on Computers ( Volume: 64, Issue: 9, 01 September 2015)
Soontae Kim
Paper:
IEEE TC 2015
Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho
IEEE Transactions on Computers ( Volume: 64, Issue: 6, 01 June 2015)
Paper:
2014
ICCD 2014
Ternary cache: Three-valued MLC STT-RAM caches
2014 IEEE 32nd International Conference on Computer Design (ICCD)
Paper:
2013
HPCA 2013
Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
Paper:
HPCA 2013
Skinflint DRAM system: Minimizing DRAM chip writes for low power
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
Paper:
DATE 2013
AVICA: An access-time variation insensitive L1 cache architecture
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Soontae Kim
Paper:
2011
MICRO 2011
Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits
MICRO-44: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Paper:
LPED 2011
TLB index-based tagging for cache energy reduction
IEEE/ACM International Symposium on Low Power Electronics and Design
Paper:
2010
ICCD 2010
Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU
2010 IEEE International Conference on Computer Design
Soontae Kim
Paper:
2009
ISVLSI 2009
TEPS: Transient Error Protection Utilizing Sub-word Parallelism
2009 IEEE Computer Society Annual Symposium on VLSI
Soontae Kim
Paper: