https://skku-compasslab.github.io/compasslab/publications/papers/Recent content in Papers on COMPASSLABHugoen-usTue, 29 Sep 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260929-neurips-token_filtering/Tue, 29 Sep 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260929-neurips-token_filtering/Token Filtering: Efficient LLM Inference via Online Attention Pruning Based on KV Similarity Modern LLMs deliver strong performance but suffer from high inference latency and large memory footprints, especially during long-context decoding.https://skku-compasslab.github.io/compasslab/publications/papers/260806-pact-harmony/Thu, 06 Aug 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260806-pact-harmony/HARMONY: Cooperative Memory Scheduling for CXL Memory Systems CXL memory expands capacity, but the host and the CMM schedule requests using different information.https://skku-compasslab.github.io/compasslab/publications/papers/260728-cal-clover/Tue, 28 Jul 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260728-cal-clover/Abstract Wafer-scale GPUs integrate many GPU modules (GPMs) on a single wafer, but their distributed organization makes the address translation non-uniform: on an L2 TLB miss, a page table walker may fetch a leaf-level PTE from a remote GPM across the on-wafer mesh.https://skku-compasslab.github.io/compasslab/publications/papers/260720-cal-neuromta/Fri, 17 Jul 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260720-cal-neuromta/Abstract Multi-Tile Accelerators (MTAs) have emerged as a promising paradigm to scale the computational throughput of NPUs for modern deep learning workloads.https://skku-compasslab.github.io/compasslab/publications/papers/260720-cal-secure-tieredmem/Fri, 17 Jul 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260720-cal-secure-tieredmem/Abstract Securing CXL-based tiered memory introduces substantial overhead. To ensure the confidentiality, integrity, and freshness of data stored in CXL memory, transmitting security metadata over the CXL link consumes link bandwidth and increases memory access latency.https://skku-compasslab.github.io/compasslab/publications/papers/260712-tpds-spars/Sun, 12 Jul 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260712-tpds-spars/Abstract With the increasing deployment of Convolutional Neural Networks (CNNs) in mission-critical and safety-critical applications, ensuring fault tolerance during model inference has become a critical requirement.https://skku-compasslab.github.io/compasslab/publications/papers/260710-micro-cato/Wed, 08 Jul 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260710-micro-cato/Don’t Get Stuck in Traffic: A Case for Contention-Aware Translation Offloading CXL-attached memory (CMM) is becoming the standard way to scale memory capacity beyond the limits of DDR channels.https://skku-compasslab.github.io/compasslab/publications/papers/260420-date-boosting-llc/Mon, 20 Apr 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260420-date-boosting-llc/Abstract Modern server-grade GPUs (e.g., NVIDIA A100) integrate hundreds of cores and tens of memory partitions, providing massive compute capability and memory bandwidth.https://skku-compasslab.github.io/compasslab/publications/papers/260420-date-braid-zns/Mon, 20 Apr 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260420-date-braid-zns/Abstract Zoned Namespace (ZNS) SSD is an emerging storage solution that reduces device-level garbage collection in conventional SSDs with a block interface.https://skku-compasslab.github.io/compasslab/publications/papers/260420-date-lupin/Mon, 20 Apr 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260420-date-lupin/Abstract The rapid growth of Large Language Models (LLMs) exceeds on-chip memory capacity during inference, causing frequent external memory access and bandwidth limitations that hinder data transfer efficiency and overall performance.https://skku-compasslab.github.io/compasslab/publications/papers/260420-date-scrooge/Mon, 20 Apr 2026 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/260420-date-scrooge/Abstract Large Language Models (LLMs) have demonstrated remarkable performance in natural language processing and are now widely adopted in diverse applications.https://skku-compasslab.github.io/compasslab/publications/papers/250802-iccd-ddlm/Sat, 02 Aug 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250802-iccd-ddlm/Abstract Modern data-centric workloads are driving rapid growth in the demand for high-bandwidth, large-capacity memory. Compute Express Link (CXL) has emerged as a key technology for scalable memory expansion through the Peripheral Component Interconnect Express (PCIe)’s high-speed serial interfaces.https://skku-compasslab.github.io/compasslab/publications/papers/250802-ieee-isar-image-generation/Sat, 02 Aug 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250802-ieee-isar-image-generation/Abstract With the growing threats posed by small airborne platforms such as drones in modern warfare, there is an increasing demand for small target identification technology.https://skku-compasslab.github.io/compasslab/publications/papers/250802-pact-librapim/Sat, 02 Aug 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250802-pact-librapim/LibraPIM: Dynamic Load Rebalancing to Maximize Utilization in PIM-Assisted LLM Inference Systems “Balance is the New Speed” The proliferation of Large Language Models (LLMs) has been a key driver of the AI revolution, and to run them efficiently, modern systems use heterogeneous architectures that combine xPUs (like GPUs/NPUs) with Processing-in-Memory (PIM).https://skku-compasslab.github.io/compasslab/publications/papers/250802-iccd-minimizereaddisturb/Sat, 02 Aug 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250802-iccd-minimizereaddisturb/Abstract To meet the increasing demand for higher storage density, modern NAND flash-based SSDs employ Quad-Level Cell (QLC) technology, which stores four bits per memory cell.https://skku-compasslab.github.io/compasslab/publications/papers/250715-micro-clap/Tue, 15 Jul 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250715-micro-clap/Abstract While the multi-chip module (MCM) design allows GPUs to scale compute and memory capabilities through multi-chip integration, it also introduces memory system non-uniformity, particularly when a thread accesses resources in remote chiplets.https://skku-compasslab.github.io/compasslab/publications/papers/250715-micro-softwalker/Tue, 15 Jul 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250715-micro-softwalker/SoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications Modern GPUs are the powerful engines behind today’s most demanding applications, from AI and scientific computing to stunning graphics.https://skku-compasslab.github.io/compasslab/publications/papers/250707-itc_cscc-partitioned_llcache/Mon, 07 Jul 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250707-itc_cscc-partitioned_llcache/Abstract For increased computing capability with the need for high parallelism, data-center GPUs (A100, H100, etc.) make their architecture more efficient by splitting Network-on-Chip (NoC) into two partitions to improve local bandwidth.https://skku-compasslab.github.io/compasslab/publications/papers/250707-itc_cscc-outliermatters/Mon, 07 Jul 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250707-itc_cscc-outliermatters/Abstract As transformer-based Large Language Models (LLMs) grow, deploying them under resource constraints has become increasingly complex, making quantization a vital technique for efficient inference.https://skku-compasslab.github.io/compasslab/publications/papers/250707-itc_cscc-tournamentwarp/Mon, 07 Jul 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250707-itc_cscc-tournamentwarp/Abstract Warp scheduling policies have been extensively studied to improve GPU performance, with each policy optimized for different workload characteristics. However, current GPUs typically support only a fixed or minor parameter-tuned scheduling policy in hardware, limiting performance across diverse applications.https://skku-compasslab.github.io/compasslab/publications/papers/250707-itc_cscc-compression_znsssd/Mon, 07 Jul 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250707-itc_cscc-compression_znsssd/Abstract Conventional block interface-based SSDs, performing page-level write operations with out-of-place write policy, lead to issues such as Garbage Collection and Write Amplification.https://skku-compasslab.github.io/compasslab/publications/papers/250625-isca-avalanche/Wed, 25 Jun 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250625-isca-avalanche/Abstract Sparse Matrix Multiplication (SpMM) is essential in various scientific and engineering applications but poses significant challenges due to irregular memory access patterns.https://skku-compasslab.github.io/compasslab/publications/papers/250622-dac-pimpal/Sun, 22 Jun 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250622-dac-pimpal/PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup Following the development of technology, the computing devices becomes much faster while the memory have larger capacity.https://skku-compasslab.github.io/compasslab/publications/papers/250401-iceic-datacompression/Tue, 01 Apr 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250401-iceic-datacompression/Abstract Modern NAND Flash-based SSDs have become a cornerstone of modern data storage solutions due to their speed and efficiency. With the increasing demand for large-scale datasets to train deep learning models, the need for greater storage capacity is also on the rise.https://skku-compasslab.github.io/compasslab/publications/papers/250401-iceic-microscaling/Tue, 01 Apr 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250401-iceic-microscaling/Abstract With advances in neural network technology, Processing-In-Memory (PIM) has emerged as a solution to per-formance bottlenecks between processors and memory.https://skku-compasslab.github.io/compasslab/publications/papers/250331-date-buddy/Mon, 31 Mar 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250331-date-buddy/Abstract As Compute Express Link (CXL) emerges as a key memory interconnect, interest in optimization opportunities and challenges has grown. However, due to the different characteristics of the CXL Memory Module (CMM) compared to traditional DRAM-based Dual In-line Memory Modules (DIMMs), existing optimizations may not be effectively applied.https://skku-compasslab.github.io/compasslab/publications/papers/250331-date-tdc/Mon, 31 Mar 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250331-date-tdc/Abstract This paper proposes a novel caching mechanism for PTE pages to enhance the Tagless DRAM Cache architecture and improve address translation in large in-package DRAM caches.https://skku-compasslab.github.io/compasslab/publications/papers/250331-date-spb/Mon, 31 Mar 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250331-date-spb/Abstract Compute Express Link (CXL) is an advanced inter- connect standard designed to facilitate high-speed communication between CPUs, accelerators, and memory devices, making it wellsuited for data-intensive applications such as machine learning and real-time analytics.https://skku-compasslab.github.io/compasslab/publications/papers/250331-date-zebra/Mon, 31 Mar 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250331-date-zebra/Abstract Vision Transformers (ViTs) have achieved remarkable performance in computer vision, but their computational complexity and challenges in optimizing memory bandwidth limit hardware acceleration.https://skku-compasslab.github.io/compasslab/publications/papers/250116-ieee-dontcache/Thu, 16 Jan 2025 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/250116-ieee-dontcache/Abstract Address translation using a logical-to-physical (L2P) mapping table is essential for the NAND Flash-based SSDs. Unfortunately, the L2P mapping table size increases as SSD capacity increases.https://skku-compasslab.github.io/compasslab/publications/papers/241102-icce-asia-impact/Sat, 02 Nov 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/241102-icce-asia-impact/Abstract As data processing requirements and memory de-mands driven by Machine Learning, Artificial Intelligence, and In-Memory Database technologies continue to grow exponentially, the need for systems with greater memory capacity is increasing.https://skku-compasslab.github.io/compasslab/publications/papers/241101-micro-avartar/Fri, 01 Nov 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/241101-micro-avartar/A Case for Speculative Address Translation with Rapid Validation for GPUs Modern GPUs rely on a unified address space to efficiently share data with CPUs, but this comes at a cost.https://skku-compasslab.github.io/compasslab/publications/papers/241101-micro-dpt/Fri, 01 Nov 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/241101-micro-dpt/Abstract Virtual memory systems rely on the page table,a crucial component that maps virtual addresses to physical addresses (i.e., address translation).https://skku-compasslab.github.io/compasslab/publications/papers/241013-pact-rethinkingpagetable/Sun, 13 Oct 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/241013-pact-rethinkingpagetable/Rethinking Page Table Structure for Fast Address Translation in GPUs: A Fixed-Size Hashed Page Table Modern GPUs rely on multi-level Radix Page Tables (RPTs) to translate virtual addresses, but irregular applications incur frequent TLB misses and sequential pointer-chasing walks that severely degrade performance.https://skku-compasslab.github.io/compasslab/publications/papers/240819-isocc-migirationrowhammer/Mon, 19 Aug 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/240819-isocc-migirationrowhammer/https://skku-compasslab.github.io/compasslab/publications/papers/240819-isocc-faulttolerance/Mon, 19 Aug 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/240819-isocc-faulttolerance/https://skku-compasslab.github.io/compasslab/publications/papers/240702-itccscc-l2pmap/Tue, 02 Jul 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/240702-itccscc-l2pmap/https://skku-compasslab.github.io/compasslab/publications/papers/240623-dac-dontcache/Sun, 23 Jun 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/240623-dac-dontcache/https://skku-compasslab.github.io/compasslab/publications/papers/240525-sa-vector/Sat, 25 May 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/240525-sa-vector/Abstract Conventional DNN inference accelerators are designed with a few (up to four) large systolic arrays. As such a scale-up architecture often suffers from low utilization, a scale-out architecture, in which a single accelerator has tens of pods and each pod has a small systolic array, has been proposed.https://skku-compasslab.github.io/compasslab/publications/papers/240109-secded/Tue, 09 Jan 2024 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/240109-secded/Abstract Racetrack memory (RM), a highly dense and high-speed spintronic non-volatile memory (NVM) technology, has the potential to revolutionize data storage.https://skku-compasslab.github.io/compasslab/publications/papers/231111-facto-cnn/Sat, 11 Nov 2023 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/231111-facto-cnn/Abstract Convolutional neural networks (CNNs) are becoming deeper and wider to achieve higher accuracy and lower loss, significantly expanding the computational resources.https://skku-compasslab.github.io/compasslab/publications/papers/231106-conveyor-sa/Mon, 06 Nov 2023 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/231106-conveyor-sa/Abstract Systolic array (SA) architecture efficiently offers parallel computation using a simple data movement across processing elements. However, their rigid structure and synchronous dataflow limit flexibility in handling sparse computations, resulting in underutilized resources and suboptimal performance.https://skku-compasslab.github.io/compasslab/publications/papers/231025-stt-ram/Wed, 25 Oct 2023 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/231025-stt-ram/Abstract DNN inference on mobile and edge devices is challenging due to high computational and storage demands. To accelerate the inference on these devices, various DNN accelerators have been proposed.https://skku-compasslab.github.io/compasslab/publications/papers/231021-sparseft/Sat, 21 Oct 2023 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/231021-sparseft/Abstract Graphics Processing Units (GPUs), while offering exceptional performance for CNN inference tasks, are susceptible to both transient and permanent hardware faults due to the integration of numerous processing elements and advancements in technology scaling.https://skku-compasslab.github.io/compasslab/publications/papers/230709-dac-cran/Sun, 09 Jul 2023 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/230709-dac-cran/https://skku-compasslab.github.io/compasslab/publications/papers/230625-caesar/Sun, 25 Jun 2023 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/230625-caesar/Abstract Convolutional Neural Networks (CNN) have shown outstanding performance in many computer vision applications. However, CNN Inference on mobile and edge devices is challenging due to high computation demands.https://skku-compasslab.github.io/compasslab/publications/papers/230625-in-cache/Sun, 25 Jun 2023 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/230625-in-cache/Abstract Convolutional Neural Networks (CNN) demand high computational capabilities, motivating researchers to leverage Processing-In-Memory (PIM) technology to achieve significant performance improvements.https://skku-compasslab.github.io/compasslab/publications/papers/230625-why-address/Sun, 25 Jun 2023 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/230625-why-address/Abstract The use of NAND Flash-based SSD is on the rise in various domains such as Enterprise, Data centers, Personal computers, and Automotive.https://skku-compasslab.github.io/compasslab/publications/papers/230222-on-the-positional/Thu, 23 Feb 2023 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/230222-on-the-positional/Abtract In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire.https://skku-compasslab.github.io/compasslab/publications/papers/221026-pinning-page/Wed, 26 Oct 2022 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/221026-pinning-page/Abstract As the memory footprint of emerging applications continues to increase, the address translation becomes a critical performance bottleneck owing to frequent misses on the Translation Lookaside Buffer (TLB).https://skku-compasslab.github.io/compasslab/publications/papers/221026-virtual-pte/Wed, 26 Oct 2022 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/221026-virtual-pte/Abstract Address translation is one of the major performance bottlenecks for emerging big data workloads. Since those workloads have large memory footprints and irregular memory access patterns, they suffer from frequent TLB (Translation Lookaside Buffer) misses and frequently incur expensive page walk.https://skku-compasslab.github.io/compasslab/publications/papers/220720-on-the-fly/Wed, 20 Jul 2022 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/220720-on-the-fly/Abstract Many deep learning frameworks utilize GEneral Matrix Multiplication (GEMM)-based convolution to accelerate CNN execution. GEMM-based convolution provides faster convolution yet requires a data conversion process called lowering (i.https://skku-compasslab.github.io/compasslab/publications/papers/220310-dac-sttmram/Thu, 10 Mar 2022 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/220310-dac-sttmram/Abstract Among the various NVM technologies, phase-change-memory (PCM) has attracted substantial attention as a candidate to replace the DRAM for next-generation memory.https://skku-compasslab.github.io/compasslab/publications/papers/220310-dont-open-row/Thu, 10 Mar 2022 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/220310-dont-open-row/Abstract Among the various NVM technologies, phase-change-memory (PCM) has attracted substantial attention as a candidate to replace the DRAM for next-generation memory.https://skku-compasslab.github.io/compasslab/publications/papers/220310-proactively/Thu, 10 Mar 2022 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/220310-proactively/Abstract Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for on-chip caches. It has a low read access time and low leakage power.https://skku-compasslab.github.io/compasslab/publications/papers/220112-exploiting-data/Wed, 12 Jan 2022 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/220112-exploiting-data/Abstract STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC).https://skku-compasslab.github.io/compasslab/publications/papers/211229-a-case-study/Wed, 29 Dec 2021 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/211229-a-case-study/Abstract Recently, the amount of attention paid towards convolutional neural networks (CNN) in medical image analysis has rapidly increased since they can analyze and classify images faster and more accurately than human abilities.https://skku-compasslab.github.io/compasslab/publications/papers/210831-exploiting-hardware/Tue, 31 Aug 2021 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/210831-exploiting-hardware/Abstract This paper proposes a novel mechanism called Event-driven Uncore Frequency Scaler (eUFS) to improve the energy efficiency of the HPC systems.https://skku-compasslab.github.io/compasslab/publications/papers/210701-cid/Thu, 01 Jul 2021 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/210701-cid/Abstract Code compression is widely used to reduce the footprint of code memory in cost-sensitive embedded systems. However, despite the small code size, the decompressor and the address translator required to support the code compression incur energy and area overheads.https://skku-compasslab.github.io/compasslab/publications/papers/210131-proactive-dead/Sun, 31 Jan 2021 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/210131-proactive-dead/Abstract Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for the on-chip caches. It has low read access time and low leakage power.https://skku-compasslab.github.io/compasslab/publications/papers/201018-adam/Sun, 18 Oct 2020 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/201018-adam/Abstract Spin-Transfer Torque Random Access Memory (STT-RAM) is a potential alternative for SRAM-based on-chip caches. STT-RAM offers high density and low leakage power, thereby can be used to build a large capacity last-level caches (LLC).https://skku-compasslab.github.io/compasslab/publications/papers/200429-dynamic-rank/Wed, 29 Apr 2020 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/200429-dynamic-rank/Abstract In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression.https://skku-compasslab.github.io/compasslab/publications/papers/200331-dead-block/Tue, 31 Mar 2020 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/200331-dead-block/Abstract In this paper, we propose an efficient adaptive write scheme that improves the performance of write operation in MLC STT-MRAM caches.https://skku-compasslab.github.io/compasslab/publications/papers/191218-analyzing/Wed, 18 Dec 2019 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/191218-analyzing/Abstract 메인 메모리의 데이터를 각종 보안공격으로부터 보호하는 것은 매우 중요하다. 최근 Counter-mode 암호화 기법을 적용하여 memory의 보안성을 향상시킨 secure memory 기술이 제안되었다.https://skku-compasslab.github.io/compasslab/publications/papers/191218-rna/Wed, 18 Dec 2019 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/191218-rna/Abstract 생물체의 유전자에서 발현되는 전사체를 분석하면 내부 유전적 병변 또는 외부 자극 및 변화하는 환경에 대한 세포반응을 알 수 있으며, 이를 통해 유전병 또는 암과 같은 질병을 야기하는 유전자군 발굴이 가능하다.https://skku-compasslab.github.io/compasslab/publications/papers/191012-touche/Sat, 12 Oct 2019 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/191012-touche/Abstract Compression is seen as a simple technique to increase the effective cache capacity. Unfortunately, compression techniques either incur tag area overheads or restrict cache block placement to only include neighboring addresses.https://skku-compasslab.github.io/compasslab/publications/papers/190404-split-cnn/Thu, 04 Apr 2019 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/190404-split-cnn/Abstract We present an interdisciplinary study to tackle the memory bottleneck of training deep convolutional neural networks (CNN). Firstly, we introduce Split Convolutional Neural Network (Split-CNN) that is derived from the automatic transformation of the state-of-the-art CNN models.https://skku-compasslab.github.io/compasslab/publications/papers/190315-interpage/Fri, 15 Mar 2019 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/190315-interpage/Abstract During the past decade, the endurance of NAND flash memory has severely deteriorated. The maximum number of program and erase cycles has fallen significantly with emerging of multilevel cell (MLC) and triple-level cell (TLC) technology, and scaling down of the cell size.https://skku-compasslab.github.io/compasslab/publications/papers/181020-attache/Sat, 20 Oct 2018 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/181020-attache/Abstract Memory systems are becoming bandwidth constrained and data compression is seen as a simple technique to increase their effective bandwidth.https://skku-compasslab.github.io/compasslab/publications/papers/171002-cramsim/Mon, 02 Oct 2017 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/171002-cramsim/Abstract The explosion of digital data and the high computation demands of data analysis have made the memory system a major contributor to the performance and power consumption of modern computing systems.https://skku-compasslab.github.io/compasslab/publications/papers/170204-partial-row/Sat, 04 Feb 2017 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/170204-partial-row/Abstract Owing to increasing demand of faster and larger DRAM system, the DRAM system accounts for a large portion of the total power consumption of computing systems.https://skku-compasslab.github.io/compasslab/publications/papers/160101-designing/Fri, 01 Jan 2016 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/160101-designing/Abstract Continuous scaling of process technology increases variations in transistors. The process variations cause large fluctuations in the access times of static random-access memory (SRAM) cells.https://skku-compasslab.github.io/compasslab/publications/papers/150901-a-low-cost-mechanism/Tue, 01 Sep 2015 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/150901-a-low-cost-mechanism/Abstract Digital circuits are expected to increasingly suffer from more hard faults due to technology scaling. Especially, a single hard fault in ALU (Arithmetic Logic Unit) might lead to a total failure in processors or significantly reduce their performance.https://skku-compasslab.github.io/compasslab/publications/papers/140716-ensuring-cache/Tue, 01 Sep 2015 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/140716-ensuring-cache/Abstract Nanoscale process variations in conventional SRAM cells are known to limit voltage scaling in microprocessor caches. Recently, a number of novel cache architectures have been proposed which substitute faulty words of one cache line with healthy words of others, to tolerate these failures at low voltages.https://skku-compasslab.github.io/compasslab/publications/papers/141019-ternary-cache/Sun, 19 Oct 2014 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/141019-ternary-cache/Abstract Spin-transfer torque random access memory (STT-RAM) has become a promising non-volatile memory technology for cache memories. Recently, 2-bit multi-level cell (MLC) STT-RAM has been proposed to enhance data density, but it suffers from low reliability of its read and write operations.https://skku-compasslab.github.io/compasslab/publications/papers/130318-avica/Mon, 18 Mar 2013 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/130318-avica/Abstract Ever scaling process technology increases variations in transistors. The process variations cause large fluctuations in the access times of SRAM cells.https://skku-compasslab.github.io/compasslab/publications/papers/130223-macho/Sat, 23 Feb 2013 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/130223-macho/Abstract Recent interest in CMOS voltage scaling has produced a class of cache architectures which tolerate parametric SRAM failures at low voltage by substituting faulty words of one cache line with healthy words of another line.https://skku-compasslab.github.io/compasslab/publications/papers/130223-skinflint/Sat, 23 Feb 2013 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/130223-skinflint/Abstract DRAMs are one of the main players of computer system energy consumption due to their large capacities and frequent accesses.https://skku-compasslab.github.io/compasslab/publications/papers/111203-residue-cache/Sat, 03 Dec 2011 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/111203-residue-cache/Abstract L2 cache memories are being adopted in the embedded systems for high performance, which, however, increases energy consumption due to their large sizes.https://skku-compasslab.github.io/compasslab/publications/papers/110801-tlb-index-based/Mon, 01 Aug 2011 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/110801-tlb-index-based/Abstract Conventional cache tag matching is based on addresses to identify correct data in caches. However, this tagging scheme is not efficient because tag bits are unnecessarily large.https://skku-compasslab.github.io/compasslab/publications/papers/101003-lizard/Sun, 03 Oct 2010 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/101003-lizard/Abstract Digital circuits are expected to increasingly suffer from more hard faults due to technology scaling. Especially, a single hard fault in the ALU might lead to a total failure in the embedded systems.https://skku-compasslab.github.io/compasslab/publications/papers/090313-teps/Fri, 13 Mar 2009 00:00:00 +0000https://skku-compasslab.github.io/compasslab/publications/papers/090313-teps/Abstract Future microprocessors are expected to observe higher transient error rates in combinational logic due to technology scaling and dense integration.